Semiconductor device having semiconductor regions of different conductivity types isolated by field oxide, and method of manufacturing the same

ABSTRACT

A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.

BACKGROUND OF THE INVENTION

1. This invention relates to a semiconductor device and a method ofmanufacturing the same. More particularly, the present invention relatesto an isolation technology in semiconductor devices such as a DRAM, anEEPROM, etc.

2. With further miniaturization of elements in semiconductor devices, anisolation method has become one of the critical problems to be overcome.A method known as local oxidation of silicon (LOCOS) has been widelyused as the isolation method. When isolation is carried out by thisLOCOS method, however, bird's beaks develop and limit the area offorming elements such as transistors. Therefore, this method cannoteasily satisfy a higher integration density of semiconductor devicesrequired recently. A so-called “field-shield isolation” method, whichisolates elements by a MOS structure formed on a semiconductorsubstrate, has been proposed as an isolation method which does notgenerate the bird's beaks.

3. Generally, the field-shield isolation structure has a MOS structurein which shield gate electrodes made of a polycrystalline silicon(poly-silicon) film are formed over a silicon substrate through a shieldgate oxide film. This shield gate electrode is always kept at a constantpotential of 0 V, for example, as it is grounded (GND) through aconnection conductor when the silicon substrate (or a well region) has aP type conductivity. When the silicon substrate (or the well region) hasan N type conductivity, the shield gate electrode is always kept at apredetermined potential (a power source potential Vcc [V], for example).

4. As a result, because the formation of a channel of a parasitic MOStransistor on the surface of the silicon substrate immediately below theshield gate electrode can be prevented, adjacent elements such astransistors can be electrically isolated from one another. According tothis field-shield isolation, ion implantation for forming the channelstopper which has been necessary for the LOCOS is not necessary. Inconsequence, a narrow channel effect of the transistor can be reducedand the substrate concentration can be lowered, so that the junctioncapacitance formed inside the substrate becomes small, and the operationspeed of the transistor can be improved.

5. JP-A-61-75555 (laid-open on Apr. 17, 1986 and corresponding to U.S.Ser. No. 626,572 filed Jul. 2, 1984 with U.S. PTO) discloses asemiconductor device employing a field-shield structure or field oxidefilm for isolation between elements.

6. JP-A-63-305548 (laid-open on Dec. 13, 1988) discloses a semiconductordevice in which a field oxide film is formed on an n-type semiconductorregion and a field-shield structure is formed on a p-type semiconductorregion.

SUMMARY OF THE INVENTION

7. As a result of researches and investigations conducted by the presentinventors, it has been found with the field-shield isolation structurethat inconveniences are encountered when it is required to form wells tobe fixed or kept at different potentials for the purpose of forming acircuit such as a CMOS circuit, as will be described below.

8. Generally, in a CMOS circuit, a P-type well in which an N-type MOStransistor is formed is kept at the ground potential, while an N-typewell in which a P-type MOS transistor is formed is kept at a powersupply potential. Thus, a shield gate electrode for isolation of theN-type MOS transistor in the P-type well must be also kept at the groundpotential, and a shield gate electrode for isolation of the P-type MOStransistor in the N-type well must be also kept at the power supplypotential for isolation of the transistor elements. Therefore, it isimpossible to directly connect to either a shield electrode for theN-type well or a shield electrode for the P-type well a shield gateelectrode which serves to isolate elements near a junction between theP-type well and the N-type well, one in the P-type well and the other inthe N-type well. This necessitates formation of an isolating activeregion at the junction of the N-type and P-type wells. As a result,direct connection of the gates of the N-type and P-type MOS transistorswith a poly-silicon becomes impossible, and additional connectionconductors have to be provided at a higher level for the connection ofthe gates of the transistors.

9. Due to the above-mentioned structural limitations, a large area isneeded to impede a high integration of the circuit, and furtherreliability of a multi-layer connection structure need to be ensured,which will make the production cost higher.

10. It is therefore an object of the present invention to provide asemiconductor device having an isolation structure which is useful forintegrating semiconductor elements or circuit elements at a highintegration density and reducing a chip area, and a method ofmanufacturing such a semiconductor device.

11. It is another object of the present invention to provide asemiconductor device in which two element formation regions orsemiconductor regions having different conductivity types can beisolated from each other by an isolation structure having a smaller sizethan those of the prior art devices, and a method of manufacturing sucha semiconductor device.

12. It is still another object of the present invention to provide asemiconductor device in which electrical connection is possible betweenelements formed at the boundary between two element formation regions orsemiconductor regions having different conductivity types by anintegrated (single) connection conductor, and a method of manufacturingsuch a semiconductor device.

13. According to one aspect of the present invention, a field oxide filmis formed at a main surface of a semiconductor substrate, the fieldoxide film having an inner surface located within the semiconductorsubstrate, and a junction formed between two semiconductor regions ofdifferent conductivity types defined in the semiconductor substrateterminates at the inner surface of the field oxide film. By thisstructure, the semiconductor regions of different conductivity types areisolated from each other, and it is possible to form a conductorextending on the isolating field oxide film for making electricalconnection between circuit elements in the isolated semiconductorregions.

14. According to another aspect of the present invention, in asemiconductor device of the type in which a first well region of a firstconductivity type and a second well region of a second conductivitytype, that are fixed at mutually different potentials, are formedadjacent to each other in a surface portion of a semiconductor regionand a plurality of MOS transistors each having source/drain regions ofan opposite conductivity type to that of each well are formed in atleast one of the first and second regions, these MOS transistors areelectrically isolated from one another by a field-shield isolationstructure and the first and second regions are electrically isolatedfrom each other by a first field oxide film.

15. According to still another aspect of the present invention, in asemiconductor device including a plurality of well regions formed in asurface portion of a semiconductor substrate, these well regions areelectrically isolated from each other and from the semiconductorsubstrate by a field oxide film, and isolation of other elements isattained by field-shield isolation structures.

BRIEF DESCRIPTION OF THE DRAWINGS

16.FIG. 1 is a sectional view of a semiconductor device according to afirst embodiment of the present invention.

17.FIG. 2 is a sectional view of a typical DRAM according to a secondembodiment of the present invention.

18.FIG. 3 is a sectional view of a typical flash memory according to athird embodiment of the present invention.

19.FIG. 4 is a sectional view of another typical flash memory accordingto a fourth embodiment of the present invention.

20.FIG. 5 is a sectional view of another typical DRAM according to afifth embodiment of the present invention.

21.FIGS. 6a to 6 h are sectional views showing step-wise a method ofmanufacturing a semiconductor device according to a sixth embodiment ofthe present invention.

22.FIGS. 7a to 7 g are sectional views showing step-wise a method ofmanufacturing a semiconductor device according to a seventh embodimentof the present invention.

23.FIG. 8 is an equivalent circuit diagram of a CMOS circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

24. First, a semiconductor device inclusive of a CMOS circuit accordingto the first embodiment of the present invention will be explained withreference to FIG. 1 which is a schematic sectional view. In FIG. 1, a Pwell (PW) 101 kept at a common potential or a ground potential Vee andan N well (NW) 102 kept at a power source potential Vcc are shown formedinside a silicon substrate 100 having a main surface. N type MOStransistors 103 are formed in the P well 101 and P type MOS transistors104 are formed in the N well 102.

25. Each of the N type MOS transistors 103 includes a gate electrode 110comprising a phosphorus-doped poly-silicon film which is formed on the Pwell 101 through a gate oxide film 132 and has a film thickness of about100 to about 300 nm, and a pair of N type impurity diffusion layers 120(only one of them being shown in FIG. 1) formed inside the surface ofthe P wells 101 on both sides of the gate electrode 110 and serving asthe source and the drain. Incidentally, the reason why one of each pairof N type impurity diffusion layers 120 is shown in FIG. 1 is becausethis drawing is a sectional view along the gate electrode 110 and theother N type impurity diffusion layer 120 does not appear. This alsoholds true of the latter-appearing P type impurity diffusion layers 122.

26. The N type MOS transistors 103 are isolated by a field-shieldisolation structure having a shield gate electrode 105 having a filmthickness of about 300 to about 500 nm and crossing at right angles agate electrode 110. The shield gate electrode 105 whose periphery iscovered with a silicon dioxide film 133 comprising a sidewall oxide filmand a cap oxide film has its potential kept at the common potential suchas a ground potential Vee. Since the formation of a parasitic channel inthe P well 101 immediately below the shield gate electrode 105 can bethus prevented, the adjacent N type MOS transistors 103 can beelectrically isolated from one another.

27. Each of the P type MOS transistors 104 includes a gate electrode 111comprising a phosphorus-doped poly-silicon film formed on the N well 102through a gate oxide film 132, and having a film thickness of about 100to about 300 nm and a pair of P type impurity diffusion layers 122formed inside the surface portions of the N wells 102 on both sides ofthe gate electrode 111 and serving as the source and the drain (only oneof them being shown in FIG. 1).

28. The P type MOS transistors 104 are isolated by a field-shieldisolation structure having an about 300 to about 500 nm-thick shieldgate electrode 106 having a pattern crossing orthogonally the gateelectrodes 111. The shield gate electrode 106 whose periphery is coveredwith a silicon dioxide film 133 comprising a sidewall oxide film and acap oxide film has its potential kept at a power source potential Vcc.Since the formation of a parasitic channel in the N well 102 immediatelybelow the shield gate electrode 106 can be thus prevented, the adjacentP type MOS transistors 104 can be electrically isolated from oneanother.

29. As described above, in the semiconductor device according to thisembodiment, a plurality of N type MOS transistors 103 formed in the Pwell 101 and a plurality of P type MOS transistors 104 formed in the Nwell 102 can be electrically isolated from one another by thefield-shield isolation structure which does not invite the occurrence ofthe bird's beaks that have been observed in the LOCOS method. Therefore,a greater area can be secured for the active region of each well 101,102 than when isolation is attained by the LOCOS method. In other words,the MOS transistors 103 and 104 can be formed in a higher integrationdensity, and a semiconductor device having the CMOS structure can behighly integrated. Because ion implantation into the element isolationregions for forming the channel stopper, which has been necessary in theLOCOS method, is not required, the narrow channel effect of the MOStransistors 103 and 104 can be reduced, the concentration of each well101, 102 can be lowered and the junction capacity can be made small.Consequently, the MOS transistors 103 and 104 can be operated at a highoperation speed.

30. In the semiconductor device according to this embodiment, the fieldoxide film 114 having a film thickness of about 150 to about 500 nm isformed in such a manner as to bridge the P well 101 and the N well 102or in other words, to cross over the PN junction therebetween. The fieldoxide film has an inner surface located inside or within the substrate100. The film thickness is decided in such a manner that an inversionlayer is not formed at the position immediately below the oxide film114. This field oxide film 114 can be formed by the LOCOS method. The PNjunction terminates at the inner surface of the field oxide film 114.The P well 101 and the N well 102 are electrically isolated from oneanother by forming the thick field oxide film 114. In other words, sincethe field oxide film 114 is formed to a sufficiently large thickness, itis possible to prevent the formation of the channel below the fieldoxide film 114 and the operation of the parasitic transistor even whenthe potential of a connection conductor (e.g. gate electrodes 110 and111) formed on this field oxide film 114 changes. Therefore, even when aP type impurity diffusion layer having a relatively high impurityconcentration is not formed as has been made in the prior art, the Pwell 101 and the N well 102 can be electrically isolated from oneanother, and the width necessary for isolation can be reduced by fargreatly than in the prior art. Therefore, a semiconductor device havinga CMOS structure can be integrated in a higher integration density.

31. In the semiconductor device according to this embodiment, the activeregion to which a voltage for keeping the potentials of the wells isapplied is not formed inside the P wells 101 and the N well 102 formedadjacent to one another so as to form the PN junction. Therefore, theCMOS circuit can be constituted by directly connecting the gateelectrode 110 of each N type MOS transistor 103 and the gate electrode111 of each P type MOS transistor 104 by the conductor extending on thefield oxide film 114 (or in other words, integrally forming the two gateelectrodes 110 and 111). For this reason, a troublesome process step ofleading out the two gate electrodes 110 and 111 and indirectlyconnecting them by a leading-out electrode, etc., becomes unnecessary.Because the number of portions of multi-layered wiring decreases,reliability of wiring connection can be improved. Incidentally, powersource means not shown in FIG. 1 supplies the ground potential Vee andthe power source potential Vcc.

32. As described above, the semiconductor device according to thisembodiment uses the field-shield isolation structure to electricallyisolate a plurality of MOS transistors 103 and 104 formed in the P well101 and the N well 102 from one another, respectively, and uses thefield oxide film 114 to electrically isolate the two wells 101 and 102from each other. Therefore, the area necessary for isolation can bereduced in each of the wells 101 and 102 and in the well boundaryregion. In other words, because the MOS transistors 103 and 104 can beformed in a higher integration density, the integration density of thesemiconductor device can be improved.

33. The semiconductor device shown in FIG. 1 can be fabricated by thesteps of forming first the two wells 101 and 102 by ion implantation,forming then the field oxide film 114 by the LOCOS method, furtherforming the field-shield isolation structure by CVD or thermaloxidation, and integrally patterning the gate electrodes 110 and 111.Because the field-shield isolation structure is formed in this way afterthe field oxide film 114 is formed, the peripheral portions of theshield gate electrodes 105 and 106 are prevented from being oxidized bythe heat-treatment during the LOCOS process. However, if design is madein advance by taking into consideration the decrement of the widths ofthe shield gate electrodes 105 and 106 by this thermal oxidation, thefield oxide film 114 can be formed after the field-shield isolationstructure is formed.

34. Next, the semiconductor device according to the second embodiment ofthe present invention will be explained with reference to FIG. 2 whichis a schematic sectional view of the semiconductor device. Thisembodiment represents the application of the present invention to a DRAMhaving a CMOS circuit in a peripheral circuit region.

35. Referring to FIG. 2, a P well (PW) 201 kept at the common potentialor the ground potential Vee and an N well (NW) 202 kept at the powersource potential Vcc are shown formed inside a silicon substrate 200having a main surface. P type MOS transistors 204 constituting aperipheral circuit are formed in the N well 202. N type MOS transistors203 constituting a peripheral circuit and DRAM memory cells 241constituting a memory cell array are formed in the P well 201. The DRAMmemory cell 241 comprises a capacitor 245 which in turn comprises alower electrode 242 formed on the inter-level insulating film 248 andcomprising a poly-silicon film, a capacitance dielectric film 243covering the lower electrode 242 and comprising an ONO film, and anupper electrode 244 comprising a polycrystalline silicon film, and an Ntype MOS transistor 247 using an impurity diffusion layer 246, whichkeeps contact with the lower electrode 242, as one of the source and thedrain thereof. Incidentally, since the memory cell array region shown inFIG. 2 shows the section at the portion of the impurity diffusion layer246, the gate electrode of the MOS transistor 247 constituting thememory cell 241 is not shown in the drawing.

36. Each N type MOS transistor 203 includes a gate electrode 210 about100 to about 300 nm thick comprising a phosphorus-doped poly-siliconfilm formed on the P well 201 through a gate oxide film 232, and a pairof N type impurity diffusion layers 220 (only one of them being shown inFIG. 2) formed inside the surface of the P wells 201 on both sides ofthe gate electrode 210 and serving as the source and the drain. Thoughonly one of the pair of the N type impurity diffusion layers 220 isshown in FIG. 2 for ease of explanation, the other of the N typeimpurity diffusion layer 220 does not appear in the peripheral circuitregion in FIG. 2 because the drawing is a sectional view taken along thegate electrode 210. This also holds true of the later-appearing P typeimpurity diffusion layer.

37. The N type MOS transistors 203 and 247 are electrically isolated bya field-shield isolation structure having a shield gate electrode 205having a pattern crossing orthogonally the gate electrode 210 and a filmthickness of about 300 to about 500 nm. The shield gate electrode 205whose periphery is covered with a silicon dioxide film 233 comprising asidewall oxide film and a cap oxide film has the potential thereof keptat the ground potential Vee. Since the formation of a parasitic channelin the P well 201 immediately below the shield gate electrode 205 can bethus prevented, the adjacent N type MOS transistors 203 and 247 can beelectrically isolated from one another.

38. Each P type MOS transistor 204 includes an about 100 to 300 nm-thickgate electrode 211 comprising a phosphorus-doped poly-silicon filmformed on the N well 202 through a gate oxide film 232, and a pair of Ptype impurity diffusion layers 222 (only one of them being shown in FIG.2) formed at the surface portions of the N wells 202 on both sides ofthe gate-electrode 211 and serving as the source and the drain.

39. The P type MOS transistors 204 are electrically isolated by afield-shield isolation structure having a shield gate electrode 206about 300 to about 500 nm thick having a pattern crossing orthogonallythe gate electrode 211. The shield gate electrode 206 whose periphery iscovered with a silicon dioxide film 233 comprising a sidewall oxide filmand a cap oxide film has the potential thereof kept at the power sourcevoltage Vcc. Since the formation of a parasitic channel in the N well202 immediately below the shield gate electrode 206 can be thusprevented, the adjacent P type MOS transistors 204 can be electricallyisolated from one another.

40. As described above, in the DRAM according to this embodiment, aplurality of the N type MOS transistors 203 and 247 formed in the P well201 and a plurality of P type MOS transistors 204 formed in the N well202 are electrically isolated from one another by the field-shieldisolation structure which does not generate the bird's beaks inherent tothe LOCOS method. Therefore, the active region of each well 201, 202 canbe secured more greatly than when isolation is attained by the LOCOSmethod, and the MOS transistors 203 and 204 can be formed in a higherdensity. In other words, the DRAM having the CMOS structure can beintegrated in a higher density. Because ion implantation into theisolation region in order to form the channel stropper as has beennecessary in the LOCOS method is not required, the narrow channel effectof the MOS transistors 203, 204 and 247 can be reduced, theconcentration of each well 201, 202 can be lowered and the junctioncapacitance can be made small. In consequence, the MOS transistors 203,204 and 247 can be operated at a higher speed, and these transistors canbe operated even when the capacitance of the capacitor 241 is small.

41. In the DRAM according to this embodiment, the field oxide film 214having a film thickness of about 150 to about 500 nm is formed in such amanner as to bridge the P well 201 and the n well 202, that is, in sucha manner as to cross over the PN junction. This field oxide film has aninner surface located inside or within the substrate 200. Since thefield oxide film 214 having a film thickness sufficient to prevent theformation of an inversion layer immediately therebelow is formed in thisway, the P well 201 and the N well 202 are electrically isolated fromeach other. Further, the PN junction terminates at the inner surface ofthe field oxide film 214. In other words, since the field oxide film 214is formed to a sufficient film thickness, it becomes possible to preventthe formation of a channel below the field oxide film 214 and theoperation of the parasitic transistor even when the potential of thewiring conductor formed on this field oxide film 214 (e.g. gateelectrodes 210 and 211) changes. Therefore, even when a P type impuritydiffusion layer having a relatively high concentration, which has beennecessary in the past, is not formed, the P well 201 and the N well 202can be electrically isolated and the width necessary for isolation canbe reduced by far greatly than the prior art. In other words, the DRAMhaving the CMOS structure can be integrated in a higher integrationdensity.

42. In the DRAM according to this embodiment, further, the active regionto which the voltage is applied in order to keep the well potential isnot formed in both P well 201 and N well 202 that form the PN junctionadjacent to one another. For this reason, the CMOS circuit can beconstituted by directly connecting the gate electrode 210 of the N typeMOS transistor 203 and the gate electrode 211 of the P type MOStransistor 204 by a wiring conductor extending on the field oxide film214 (that is, by forming integrally the two gate electrodes 210 and211), and the troublesome process step of indirectly connecting the twogate electrodes 210 and 211 through a leading-out electrode, etc,becomes unnecessary. Since the number of portions of multi-layeredwiring decreases, reliability of wiring connection can be improved.Incidentally, power source means not shown in FIG. 2 supplies the groundpotential Vee and the power source potential Vcc.

43. As described above, the DRAM according to this embodiment uses thefield-shield isolation structure for electrically isolating a pluralityof MOS transistors 203, 204 and 247 formed in the P and N wells 201 and202 from one another, respectively, and uses the field oxide film 214for electrically isolating the two wells 201 and 202 from each other.According to this arrangement, the area most necessary for isolation ineach of the wells 201 and 202 and the well boundary region can bereduced. In consequence, the MOS transistors 203, 204 and 247 can beformed in a higher density, and the DRAM can be integrated in a higherintegration density.

44. Next, a flash EEPROM (flash memory) according to the thirdembodiment of the present invention will be explained with reference toFIG. 3 which is a schematic sectional view of the EEPROM. Thisembodiment represents the application of the present invention to aflash memory having a CMOS circuit in a peripheral circuit region.

45. Referring to FIG. 3, a P well (PW) 301 kept at a common potential ora ground potential Vee and an N well (NW) 302 kept at a power sourcepotential Vcc are shown formed inside a silicon substrate 300 having amain surface. P type MOS transistors 304 constituting a peripheralcircuit are formed in the N well 302 and N type MOS transistors 303constituting the peripheral circuit and stacked gate type memory cells341 constituting a memory cell array are formed in the P well 301.

46. The memory cell 341 is an N type MOS transistor which includes acomposite gate structure 345 comprising a floating gate 342 comprising apoly-silicon film formed on the P well 301 through a tunnel oxide film349, a dielectric film 343 comprising an ONO film which covers thefloating gate 342 and a control gate 344 comprising a poly-silicon film,and uses a pair of N type impurity diffusion layers 346 (only one ofthem being shown in FIG. 3) formed inside the surface portion of the Pwells 301 on both sides of the floating gate as its source and drain.Incidentally, the reason why only one of the pair of N type impuritydiffusion layers 346 is shown in FIG. 3 is because the drawing is asectional view taken along the composite gate structure 345 and the Ntype impurity diffusion layer does not practically appear in FIG. 3.This also holds true of the later-appearing N type impurity diffusionlayer 320 and the P type impurity diffusion layer 322.

47. The N type MOS transistor 303 includes a gate electrode 310comprising a phosphorus-doped poly-silicon film formed on the P well 301through a gate oxide film 332 and having a film thickness of about 100to about 300 nm and a pair of N type impurity diffusion layers 320 (onlyone of them being shown in FIG. 3) formed inside the surface of the Pwells 301 on both sides of the gate electrode 310.

48. The N type MOS transistor 303 and the memory cell 341 areelectrically isolated by a field-shield isolation structure having ashield gate electrode 305 having a pattern orthogonally crossing thegate electrode 310 and having a film thickness of about 300 to about 500nm. The shield gate electrode 305 whose periphery is covered with asilicon dioxide film 333 comprising a sidewall oxide film and a capoxide film has the potential thereof kept at the ground potential Vee.It is therefore possible to prevent the formation of a parasitic channelin the P well 301 immediately below the shield gate electrode 305 andhence, to electrically isolate the adjacent N type MOS transistors 303and the adjacent memory cells 341 from one another.

49. The P type MOS transistor 304 has a gate electrode 311 comprising aphosphorus-doped poly-silicon film formed on the N well 302 through thegate oxide film 332 and having a film thickness of about 100 to about300 nm and a pair of P type impurity diffusion layers 322 (only one ofthem being shown in FIG. 3) formed at the surface portion of the N wells302 on both sides of the gate electrode 311.

50. The P type MOS transistors 304 are isolated by the field-shieldisolation structure having a shield gate electrode 306 having a patternorthogonally crossing the gate electrode 311 and having a film thicknessof about 300 to about 500 nm. The shield gate electrode 306 whoseperiphery is covered with a silicon dioxide film 333 comprising asidewall oxide film and a cap oxide film has the potential thereof keptat the power source potential Vcc. Since the formation of the parasiticchannel in the N well 302 immediately below the shield gate electrode306 can be prevented by this structure, the adjacent P type MOStransistors 304 can be electrically isolated from one another.

51. In the flash memory according to this embodiment, a plurality of Ntype MOS transistors 303 and the memory cells 341 formed in the P well301 and a plurality of P type MOS transistors 304 formed in the N well302 are electrically isolated from one another by the field-shieldisolation structure which does not invite the occurrence of the bird'sbeaks inherent to the LOCOS method. Therefore, the active region of eachwell 301, 302 can be made greater than when isolation is attained by theLOCOS method, and the MOS transistors 303 and 304 and the memory cells341 can be formed in a higher density. In other words, the flash memoryhaving the CMOS structure can be constituted in a higher integrationdensity. Because ion implantation into isolation region for forming thechannel stopper, which has been necessary according to the LOCOS method,is not necessary, the narrow channel effect of the MOS transistors 303and 304 and the memory cell 341 can be reduced, the concentration ofeach well 301, 302 can be lowered. In consequence, the junction capacitybecomes small, and the MOS transistors 303 and 304 and the memory cell341 can be operated at a higher operation speed.

52. In the flash memory according to this embodiment, the memory cells341 are electrically isolated from one another by the field-shieldisolation structure. For this reason, the parasitic transistor does notdevelop even when a high voltage is applied to the control gate 344. Inother words, rewrite of the memory cell 341 can be executed with highefficiency by applying a high voltage to the control gate 344.

53. In the flash memory according to this embodiment, the field oxidefilm 314 having a film thickness of about 150 to about 500 nm is formedin such a manner as to bridge the P well 301 and the N well 302, thatis, in such a manner as to cross over the PN junction therebetween. Thisfield oxide film has an inner surface located inside or within thesubstrate 300. Because the field oxide film 314 having a film thicknesssufficient to prevent the formation of an inversion layer immediatelytherebelow is formed in this way, the P well 301 and the N well 302 areelectrically isolated from each other. Further, the PN junctionterminates at the inner surface of the field oxide film 314. In otherwords, because the field oxide film 314 is formed to a sufficient filmthickness, it is possible to prevent the formation of the channel belowthe field oxide film 314 and the operation of the resulting parasitictransistor even when the potential of a wiring conductor formed on thisfield oxide film 314 (for example, the gate electrodes 310 and 311)changes. In consequence, the P well 301 and the N well 302 can beelectrically isolated without forming the P type impurity diffusionlayer having a relatively high impurity concentration, which has beennecessary in the past, and the width necessary for isolation can bereduced by far more greatly than in the prior art. Accordingly, theflash memory having the CMOS structure can be integrated in a higherintegration density.

54. In the flash memory according to this embodiment, the active regionto which a voltage for keeping the well potential is not formed in bothof the P and N wells 301 and 302 adjacent to each other and constitutingthe PN junction. Therefore, the CMOS circuit can be constituted bydirectly connecting the gate electrode 310 of the N type MOS transistor303 and the gate electrode 311 of the P type MOS transistor 304 by aconductor extending on the field oxide film 314 (that is, by integrallyforming the two gate electrodes 310 and 311). Therefore, the troublesomestep of indirectly connecting the two gate electrodes 310 and 311 by aleading-out electrode can be eliminated. Further, because the number ofportions as multi-layered wiring decreases, reliability of wiringconnection can be improved. Incidentally, power source means not shownin FIG. 3 supplies the ground potential Vee and the power sourcepotential Vcc.

55. As explained above, the flash memory according to this embodimentuses the field-shield isolation structure for electrically isolating aplurality of MOS transistors 303 and 304 formed in the P and N wells 301and 302 and the memory cells 341, and uses the field oxide film 314 forelectrically isolating the two wells 301 and 302 from each other.Therefore, the area most necessary for isolation can be reduced in thewells 301 and 302 and the well boundary. In other words, since the MOStransistors 303 and 304 and the memory cells 341 can be formed in ahigher density, the flash memory can be integrated in a higherintegration density.

56. Next, a flash EEPROM (flash memory) according to the fourthembodiment of the present invention will be explained with reference toFIG. 4 which is schematic sectional view of the flash memory. Thisembodiment represents the application of the present invention to aflash memory having a CMOS circuit in a peripheral circuit region and ina negative voltage control circuit region.

57. In this embodiment, the negative voltage control circuit selectivelyapplies a negative voltage to the control gate or the source/drain ofthe memory cell transistor of the flash memory at the time of writing ofdata. By this negative voltage control circuit, the withstand voltage ofthe tunnel oxide film, etc, can be increased and reliability of thememory cell can be improved. In order to apply the negative voltage tothe control gate or the source/drain of the memory cell transistor, a Pwell 452 having a negative potential must be formed, and to electricallyisolate this P well 452 having the negative potential from the substrate400, an N well 351 encompassing the P well 452 having the negativepotential and kept at the ground potential Vee, for example, must beformed. Therefore, the flash memory according to this embodimentincludes a negative voltage control circuit whose P well 452 isencompassed by the N well 451 in addition to the peripheral circuit andthe memory cell array that have been explained with reference to FIG. 3.In other words, this flash memory constitutes a so-called “triple wellstructure” with the later-appearing P well 401.

58. In FIG. 4, a P well (PW) 401 kept at a common potential or a groundpotential Vee, an N well (NW) 402 kept at a power source potential Vccand an N well (NW) 451 kept at the ground potential Vee are formedinside a silicon substrate 400 having a main surface, and a P well (PW)452 kept at a negative potential −Vpp is formed inside the N well 451. AP type MOS transistor 404 that constitutes a peripheral circuit isformed in the N well 402. An N type MOS transistor 403 constituting theperipheral circuit is formed in the P well 401, and a stacked gate typememory cell 441 of a flash memory, that constitutes the memory cellarray, is formed, too.

59. The memory cell 441 has a composite gate structure 445 including afloating gate 442 comprising a poly-silicon film formed on the P well401 through a tunnel oxide film 449, a dielectric film 443 comprising anONO film that covers the floating gate 442, and a control gate 444comprising a poly-silicon film, and is an N type MOS transistor using apair of N type impurity diffusion layers 446 (only one of them beingshown in FIG. 4) formed inside the surface of the P wells 401 on bothsides of the floating gate 442 as the source and the drain thereof.Incidentally, one of the pair of the N type impurity diffusion layers446 is shown for ease of explanation but because FIG. 4 is a sectionalview taken along the composite gate structure 445, the other N typeimpurity diffusion layer 446 does not appear in FIG. 4. This also holdstrue of the latter-appearing impurity diffusion layers 420 and 464 and Ptype impurity diffusion layers 422 and 458.

60. The N type MOS transistor 403 includes a gate electrode 410comprising a phosphorus doped poly-silicon film formed on the P well 401through a gate oxide film 432 and having a film thickness of about 100to about 300 nm and a pair of N type impurity diffusion layers 420 (onlyone of them being shown in FIG. 4) formed inside the surface of the Pwell 401 on both sides of the gate electrode 410 and serving as thesource/drain thereof.

61. The N type MOS transistor 403 and the memory cell 441 areelectrically isolated by the field-shield isolation structure having ashield gate electrode 405 having a pattern orthogonally crossing thegate electrode 410 and having a film thickness of about 300 to about 500nm. The shield gate electrode 405 whose periphery is covered with asilicon dioxide film 433 comprising a sidewall oxide film and a capoxide film has the potential thereof kept at the ground potential Vee.Since the formation of the parasitic channel in the P well 401immediately below the shield gate electrode 405 is prevented by thisstructure, the adjacent N type MOS transistors 403 and the adjacentmemory cells 441 can be electrically isolated from one another.

62. The P type MOS transistor 404 includes a gate electrode 411comprising a phosphorus-doped poly-silicon film formed on the N well 402through a gate oxide film 432 and having a film thickness of about 100to about 300 nm, and a pair of P type impurity diffusion layers 422(only one of them being shown in FIG. 4) formed inside the surface ofthe N wells 402 on both sides of the gate electrode 411 and serving asthe source and the drain of the transistor.

63. The P type MOS transistors 404 are isolated by a field-shieldisolation structure having a shield gate electrode 406 having a patternorthogonally crossing the gate electrode 411 and a film thickness ofabout 300 to about 500 nm. The shield gate electrode 406 whose peripheryis covered with a silicon dioxide film 433 comprising a sidewall filmand a cap oxide film has the potential thereof kept at a power sourcepotential Vcc. Since the formation of a parasitic channel in the N well402 immediately below the shield gate 406 can be thus prevented, theadjacent P type MOS transistors 404 can be electrically isolated fromone another.

64. In the flash memory according to this embodiment described above, aplurality of n type MOS transistors 403 and the memory cells 441 formedin the P well 401 and a plurality of P type MOS transistors 404 formedin the N well 402 are electrically isolated from one another by thefield-shield isolation structure devoid of the occurrence of the bird'sbeaks inherent to the LOCOS method. Therefore, the active region of eachwell 401 and 402 can be made greater than when isolation is attained bythe LOCOS method, and the MOS transistors 403 and 404 as well as thememory cells 441 can be formed in a higher density. In other words, theflash memory having the CMOS structure can be highly integrated. Sincethe flash memory of this embodiment does not require ion implantationinto the isolation region for forming the channel stopper which has beennecessary in the LOCOS method, the narrow channel effect of the MOStransistors 403 and 404 and the memory cells 441 can be reduced, and theconcentration of each well 401 and 402 can be lowered, thereby reducingthe junction capacity. As a result, the MOS transistors 403 and 404 andthe memory cells 441 can be operated at a higher operation speed.

65. Further, in the flash memory according to this embodiment, thememory cells 441 are electrically isolated from one another by thefield-shield isolation structure. Therefore, even when a high voltage isapplied to the control gate 444, there is no possibility of theoccurrence of the parasitic transistor and consequently, the memory cell441 can be rewritten highly efficiently by applying a high voltage tothe control gate 444.

66. In the flash memory according to this embodiment, the field oxidefilm 414 having a film thickness of about 150 to about 500 nm is formedin such a manner as to bride the P well 401 and the N well 402 or inother words, in such a manner as to cross over the PN junctiontherebetween. This field oxide film has an inner surface located insideor within the substrate 400. Because the field oxide film 414 having athickness sufficient to prevent the formation of an inversion layerimmediately therebelow is formed, the P well 401 and the N well 402 areelectrically isolated from each other. The PN junction terminates at theinner surface of the field oxide film 414. In other words, because thefield oxide film 414 is formed to a sufficient thickness, it is possibleto prevent the formation of a channel immediately below the field oxidefilm 414 and the operation of the resulting parasitic transistor evenwhen a potential of a wiring formed on this field oxide film 414 (forexample, the gate electrodes 410 and 411) changes. Accordingly, the Pwell 401 and the N well 402 can be electrically isolated from each otherwithout forming the P type impurity diffusion layer having a relativelyhigh concentration in the P well as has been necessary in the prior art,and the width necessary for isolation can be reduced by far more greatlythan in the prior art. In consequence, the flash memory having the CMOSstructure can be integrated more highly.

67. In the flash memory according to this embodiment, the active regionto which a voltage is applied so as to keep a well potential are notformed in both the P and N wells 401 and 402 adjacently constituting thePN junction and for this reason, the CMOS circuit can be constituted bydirectly connecting the gate electrode 410 of the N type MOS transistor403 and the gate electrode 411 of the P type MOS transistor by aconductor extending on the field oxide film 414 (in other words, byintegrally forming the two grate electrodes 410 and 411). Therefore, thetroublesome process step of indirectly connecting these gate electrodes410 and 411 by a leading-out electrode, etc, becomes unnecessary.Further, since the number of portions of multi-layered wiring decreases,reliability of wiring connection can be improved.

68. On the other hand, a P type MOS transistor 453 is formed in the Nwell 451 constituting the negative voltage control circuit, and an Ntype MOS transistor 454 is formed in the P well 452.

69. The P type MOS transistor 453 includes a gate electrode 456comprising a phosphorus-doped poly-silicon film formed on the N well 451through a gate oxide film 432 and having a film thickness of about 100to about 300 nm and a pair of P type impurity diffusion layers 458 (onlyone of them being shown in FIG. 4) formed inside the surface of the Nwells 451 on both sides of the gate electrode 456 and serving as thesource and the drain of the transistor.

70. The N type MOS transistor 454 includes a gate electrode 462comprising a phosphorus-doped poly-silicon film formed on the P well 452through a gate oxide film 432 and having a film thickness of about 100to about 300 nm and a pair of N type impurity diffusion layers 464 (onlyone of them being shown in FIG. 4) formed inside the surface of the Pwells 452 on both sides of the gate electrode 462 and serving as thesource and the drain of the transistor.

71. The N type MOS transistors 454 are isolated by a field-shieldisolation structure having a shield gate electrode 471 having a patternorthogonally crossing the gate electrode 462 and having a film thicknessof about 300 to about 500 nm. The shield gate electrode 471 whoseperiphery is covered with a silicon dioxide film 433 comprising asidewall oxide film and a cap oxide film has the potential thereof keptat the negative potential −Vpp. Since the formation of a parasiticchannel in the P well 452 immediately below the shield gate electrode471 can be thus prevented, the adjacent N type MOS transistors 454 canbe electrically isolated from one another.

72. As described above, in the flash memory according to thisembodiment, a plurality of N type MOS transistors 454 formed in the Pwell 452 constituting the negative voltage control circuit areelectrically isolated from one another by the field-shield isolationstructure devoid of the occurrence of the bird's beaks inherent to theLOCOS method. Therefore, the active region of the P well 452 can beformed into a greater area than when isolation is attained by the LOCOSmethod, and the MOS transistors 454 can be fabricated in a higherdensity.

73. Further, in the flash memory according to this embodiment, the fieldoxide film 482 having a film thickness of about 150 to about 500 nm isformed in such a manner as to bridge the P well 452 and the N well 451that constitute the negative voltage control circuit, or to cross overthe PN junction therebetween. This field oxide film 482 has an innersurface located inside the substrate 400 in the same way as the fieldoxide film 414 described above. Because the field oxide film 482 havinga film thickness sufficient to prevent the formation of an inversionlayer immediately therebelow is formed in this way, the P well 452 andthe N well 451 are electrically isolated from each other. The PNjunction terminates at the inner surface of the field oxide film 482. Inother words, because the field oxide film 482 is formed to a sufficientfilm thickness, the formation of the channel below the field oxide film482 and the operation of the resulting parasitic transistor can beprevented even when the potential of a wiring conductor formed on thefield oxide film 482 (for example, the gate electrodes 456 and 462)changes. For this reason, the P well 452 and the N well 451 can beelectrically isolated from each other without forming a P type impuritydiffusion layer having a relatively high concentration in the p wellwhich has been necessary in the prior art, and the width necessary forisolation can be reduced by far more greatly than in the prior art. Inother words, the flash memory having the CMOS structure can beintegrated in a high integration density. Incidentally, this embodimentuses the field oxide film 484 in order also to electrically isolate theN well 402 kept at the power source potential Vcc from the N well 451kept at the ground potential Vee. Therefore, the width necessary forisolating them can be reduced. Incidentally, the thickness of the fieldoxide film 484 and the correlation between the two PN junctions formedbetween the wells 402 and 451 and the substrate 400 and the innersurface of the field oxide 484 are the same as those which have beenexplained already about the field oxide films 414 and 482.

74. In the flash memory according to this embodiment, the active regionto which a voltage is applied for keeping the well potential is notformed in the P well 452. Therefore, the CMOS circuit can be constitutedby directly connecting the gate electrode 462 of the N type MOStransistor 454 and the gate electrode 456 of the P type MOS transistor453 by a conductor extending on the field oxide film 482 (that is, byintegrally forming the two gate electrodes 462 and 456). In consequence,the troublesome process step can be eliminated and because the number ofportions of multi-layered wiring decreases, reliability of wiringconnection can be improved. Incidentally, power source means not shownin FIG. 4 supplies the ground potential Vee, the power source potentialVcc and the negative potential −Vpp.

75. As described above, the flash memory according to this embodimentuses the field-shield isolation structure for electrically isolating aplurality of MOS transistors 403, 404 and 454 and a plurality of memorycells 441 formed in the P wells 401 and 452 and in the N wells 402 fromone another, and uses the field oxide films 414 and 482 for isolatingthe two wells 401 and 402 and the wells 451 and 452 from one another.Therefore, the area most necessary for isolation can be reduced in thewells 401, 402, 451 and 452 and in the well boundary region, and the MOStransistors 403, 404, 453 and 454 and the memory cells 441 can befabricated in a higher density, so that the integration density of theflash memory can be further increased.

76. In the semiconductor devices according to the first to fourthembodiments of the invention described above, a plurality of wellregions are formed inside the semiconductor substrate, electricalisolation between the well regions and between the well regions and theboundary with the semiconductor substrate is attained by the field oxidefilms, respectively, and isolation of the elements in each well isattained by the field-shield isolation structure. By such structures,mutual isolation of the well regions and isolation between the wellregions and the boundary with the semiconductor substrate can beattained by a small size, and isolation between the well region andanother or the substrate can be attained by a small size, too. Further,the elements in each well can be isolated by a small size. In otherwords, because optimum isolation is made for each position, thesemiconductor device can be integrated in a higher integration density.

77. Hereinafter, the fifth embodiment of the present invention will beexplained with reference to FIG. 5.

78.FIG. 5 is a sectional view of a DRAM according to this embodiment. Inthe DRAM of this embodiment, elements are isolated by the field-shieldmethod in a memory cell array section and by the LOCOS method in aperipheral circuit section.

79. The peripheral circuit section includes a CMOS circuit constitutedby N type MOS transistors 506 formed by using a p⁺layer (P well) 504formed inside a silicon substrate 501 having a main surface and P typeMOS transistors 505 formed by using an n⁺ layer (N well) 503 formedinside the substrate 501. A source/drain connection conductor 518 isconnected to the source/drain of each transistor (not shown). Each ofthe transistors 506 and 505 has a gate electrode 508 formed on the gateoxide film 507.

80. In the peripheral circuit section in which a large number of suchCMOS circuits exist, SiO₂ films (field oxide films) 515 a and 515 bhaving a film thickness of at least about 150 nm and for example, 500nm, are formed by thermally oxidizing the surface of the siliconsubstrate 501 by the LOCOS method. The transistors 505 and 506 formed inthe peripheral circuit section, that is, the two wells 503 and 504, areelectrically isolated from each other by this SiO₂ film 515 b. Each ofthe field oxide films 515 a and 515 b has an inner surface locatedinside the substrate 501, and the PN junction between the wells 502 and503 and the PN junction between the wells 503 and 504 terminate at theinner surface of the field oxide films 515 a and 515 b, respectively. Bythis structure, the wells 502 and 503 and the wells 503 and 504 areelectrically isolated from each other, respectively.

81. The memory cell array section includes a large number of DRAM memorycells 540 each comprising one MOS transistor 525 and one capacitor 530formed in the p⁺ layer (P well) 502 formed inside the silicon substrate501.

82. Each MOS transistor 525 has a SiO₂ film 507 serving as a gate oxidefilm and a gate electrode 508 made of poly-silicon and formed on theSiO₂ film 507.

83. Each capacitor 530 comprises a cell node (lower electrode) 510connected to one of the source/drain regions (not shown) of the MOStransistor 525 at a cell node contact 516, a cell plate (upperelectrode) 511 opposing this cell node 510 and a dielectric film 529sandwiched between the cell node 510 an the cell plate 511. The othersource/drain region (not shown) is connected to a metal wiring 512 at abit contact 517.

84. In the memory cell section in which a large number of such DRAMmemory cell exist, a field-shield isolation structure is constituted bythe SiO₂ film 507, the poly-silicon film (shield gate electrode) 509,the SiO₂ film 514 and the sidewall SiO₂ film 521. The sidewall SiO₂ film521 isolates the poly-silicon film 509 from other wirings. The potentialof the poly-silicon film (shield gate electrode) 509 is kept at 0 V or a½power source voltage. Incidentally, in order to isolate the P channelMOS transistors, the potential of the poly-silicon film 509 ispreferably kept at the power source voltage or the ½power sourcevoltage. A plurality of MOS transistors 525 formed in the memory cellregion are electrically isolated by this field-shield isolationstructure 519.

85. According to this embodiment, isolation is attained by thefield-shield isolation structure 519 in the memory cell array section inwhich a plurality of N type MOS transistors 525 are formed. Therefore,in comparison with isolation by the LOCOS method, the chip area can bereduced by about 0.5 μm per transistor region. Since the memory cellarray section comprises the N type MOS transistors and almost no PNjunction exists, a guard ring having a width of about 10 μm need not beformed.

86. In the peripheral circuit section in which the P and N type MOStransistors 505 and 506 co-exist, on the other hand, isolation isattained by the thick SiO₂ film 515 formed by the LOCOS method.Therefore, a guard ring having a width of about 10 μm, which isnecessary for isolation by the field-shield isolation structure, neednot be formed.

87. As described above, this embodiment employs the field-shieldisolation structure for a relatively broad region in which only the MOStransistors of the same conductivity type exist such as the memory cellarray section, for isolation, and employs the field insulating film fora region in which the CMOS circuits are formed such as the peripheralcircuit section, for isolation. In other words, this embodiment combinesthe isolation technology by the field-shield isolation structure and theisolation technology by the SiO₂ film (field oxide film) 515 formed bythe LOCOS method in such a manner as to appropriately correspond to eachregion of the DRAM. In this way, this embodiment can drastically reducethe chip area as a whole.

88. Hereinafter, the sixth embodiment according to the present inventionwill be explained with reference to FIGS. 6a to 6 h.

89. Though this embodiment is a suitable embodiment for the method ofmanufacturing a floating gate type non-volatile semiconductor memorydevice such as an EEPROM, it can be applied to the manufacture of thesemiconductor devices explained in the first to fifth embodiments.

90. In this embodiment, impurity ions are implanted into a peripheralcircuit formation section 612 of a P type silicon substrate 611 having aspecific resistance of about 10 Ω·cm so as to form a P well 614 and an Nwell 615, and to form a P well 616 in a memory cell array formationsection 613, as shown in FIG. 6a. PN junctions between the wells 614 and615 and between the wells 615 and 616 terminate at the main surface ofthe substrate 611.

91. Next, as shown in FIG. 6b, a silicon dioxide film 617 having a filmthickness of about 20 to about 40 nm is formed on the entire surface ofthe silicon substrate 611 by thermal oxidation. A poly-silicon film 621having a film thickness of about 100 to about 200 nm is deposited ontothe entire surface of the silicon dioxide film 617 by a CVD process, anda silicon nitride film 622 having a film thickness of about 150 nm isfurther deposited to the entire surface of the poly-silicon film 621 bythe CVD process.

92. Then, the silicon nitride film 622 and the poly-silicon film 621 areremoved in a width of about 0.8 μm, for example, from the portion whichis to serve as the element isolation region of the peripheral circuitformation section 612 (inclusive of the portions in the vicinity of theboundary between the P well 614 and the N well 615) and from the portionin the vicinity of the boundary between the peripheral circuit formationsection 612 and the memory cell array formation section 613 (that is,the boundary between the N well 615 and the P well 616) byphotolithography and etching. In this way, the silicon nitride film 622and the poly-silicon film 621 are left on the entire surface of theregion of the peripheral circuit formation section 612 which is to serveas the active region and the memory cell array formation section 613.Incidentally, only the silicon nitride film 622 may be removed withoutremoving the poly-silicon film 621.

93. Next, as shown in FIG. 6c, a silicon dioxide film 623 b as a fieldoxide film and a silicon dioxide film 623 a as a field oxide film areformed at the portion which is to serve as the element isolation regionof the peripheral circuit formation section 612 and at the portion ofthe substrate inclusive of the boundary between the formation portions612 and 613, respectively, by selectively oxidizing the siliconsubstrate at a temperature of about 1,000° C. by using the siliconnitride film 622 as the oxidation prevention film having thepoly-silicon film 621 formed as the lower layer thereof.

94. Since the poly-Si buffered LOCOS method is carried out in thisembodiment as described above, the growth of the silicon dioxide film623 in the direction of the surface of the silicon substrate 611 isrestricted by the poly-silicon film 621. Therefore, the bird's beaks ofthe silicon dioxide film occur in a width of only about 0.2 μm (refer toJP-A-56-70644 laid open on Jun. 12, 1981, for example).

95. The field oxide film 623 a covers the junction between the wells 615and 616, while the field oxide film 623 b covers the PN junction betweenthe wells 614 and 615, at the main surface of the substrate 611,respectively. In other words, the PN junctions terminate at the innersurface of the field oxide films 623 a and 623 b, respectively.

96. As shown in FIG. 6d, the silicon nitride film 622 is removed by wetetching using phosphoric acid, and a silicon dioxide film 624 having afilm thickness of about 100 nm is deposited to the entire surface by theCVD method. The silicon dioxide film 624 and the poly-silicon film 621are removed from the entire surface of the peripheral circuit formationsection 612 and from the region of the memory cell array formationsection 613 to serve as the active region by photolithography andetching. As a result, a pattern of the silicon dioxde film 624 and thepoly-silicon film 621 as the shield gate electrode is left in a width ofabout 0.8 μm in only the region which is to serve as the elementisolation region of the memory cell array formation section 613.Incidentally, it is possible to leave the silicon nitride film 622 andto use this silicon nitride film 622 as the insulating film on thepoly-silicon film 621.

97. Next, as shown in FIG. 6e, a silicon dioxide film 625 having a filmthickness of about 100 nm is deposited to the entire surface by the CVDmethod, and the entire surface of this silicon dioxide film 625 is thenetched back so as to form a sidewall oxide film comprising this silicondioxide film 625 on the side surfaces of the poly-silicon film 621 andthe silicon dioxide film 624. Due to etch-back of the silicon dioxidefilm 625 at this time, the silicon dioxide film 617 is removed from theactive regions of both the peripheral circuit formation section 612 andthe memory cell array formation section 613 and the silicon substrate611 is exposed. Incidentally, the poly-silicon film 621 which is toserve as the shield gate electrode is connected so as to attain the samepotential as the P well 616 in the subsequent process step, so thatisolation by the field-shield method is accomplished in the memory cellarray formation section 613. Incidentally, FIG. 6e shows the silicondioxide film 623 a formed in the vicinity of the boundary between the Nwell 615 and the P well 616 in such a manner that it keeps contact withthe isolation structure using the poly-silicon film 621 as the shieldgate electrode, but the silicon dioxide film 623 a need not be alwaysformed in this way. In other words, the silicon dioxide film 623 a andthe isolation structure using the poly-silicon film 621 may be spacedapart from each other.

98. Next, a silicon dioxide film 626 to serve as a gate oxide film or atunnel oxide film is formed on the surface of the exposed siliconsubstrate 611 by thermally oxidizing this surface, as shown in FIG. 6f.Therefore, a floating gate in the memory cell array formation section613 is formed by using an N type poly-silicon film 627, and acapacitance dielectric film for the floating gate and the control gateis formed by using an ONO film (silicon dioxide film/silicon nitridefilm/silicon dioxide film). Incidentally, the silicon dioxide film 626to be formed in the peripheral circuit formation section 612 and thesilicon dioxide film 626 to be formed in the memory cell array formationsection 613 having mutually different film thickness may be formed byseparate process steps.

99. The gate electrode in the peripheral circuit formation section 612and the control gate in the memory cell array formation section 613 arethen formed by using the N type poly-silicon film 632. In this instance,the gate electrode in the peripheral circuit formation section 612 maybe formed by using both of the poly-silicon films 627 and 632, or byusing only the poly-silicon film 627.

100. Next, as shown in FIG. 6g, N type impurity ions are implanted intothe P well 614 of the peripheral circuit formation section 612 and intothe memory cell array formation section 613 so as to form a pair of Ntype impurity diffusion layers 633 on both sides of the poly-siliconfilm 632. Further, P type impurity ions are implanted into the N well615 of the peripheral circuit formation section 612 to form P typeimpurity diffusion layers 634 on both sides of the poly-silicon film632. In this way, the N type MOS transistor 635 and the P type MOStransistor 636 together constituting a CMOS circuit are completed in theperipheral circuit formation section 612 while the memory celltransistor 637 is completed in the memory cell array formation section613. Thereafter, an inter-level insulating film 641 is formed on theentire surface.

101. Next, a contact hole 642 is bored in the inter-level insulatingfilm 641 in such a manner as to reach the N type impurity diffusionlayer 633 and the P type impurity diffusion layer 634 as shown in FIG.6h. An aluminum (Al) wiring 643 is then patterned so that it can beconnected to the N type impurity diffusion layer 633 and the P typeimpurity diffusion layer 634 in the contact hole 642. Furthermore, asurface protective film (not shown), etc, is formed, and a non-volatilesemiconductor memory device having the CMOS circuit in the peripheralcircuit section 612 and the floating gate memory cell transistors 637 inthe memory cell array formation section 613 can be completed.

102. As described above, since this embodiment uses the poly-siliconfilm 621, which is formed as the buffer layer when the poly-Si bufferedLOCOS method is carried out, as the shield gate electrode in the memorycell array formation section 613, it does not require to afresh form aconductor film such as a new poly-silicon film so as to form the shieldgate electrode, and can therefore reduce the number of the processsteps.

103. Though this embodiment represents the application of the presentinvention to the manufacture of the non-volatile semiconductor memorydevice having the floating gate type memory cell transistors, thepresent invention can be likewise applied to the manufacture ofnon-volatile semiconductor memory devices having memory cell transistorsof types other than the floating gate type and semiconductor devicesother than the non-volatile semiconductor memory device such as DRAMS.

104. Next, the seventh embodiment of the present invention will beexplained with reference to FIGS. 7a to 7 g. This embodiment representsa preferred embodiment of the invention relating to the method ofmanufacturing a one-transistor one-capacitor type DRAM, but it can besimilarly applied to the manufacture of the semiconductor devicesexplained with reference to the first to fifth embodiments.

105. The DRAM to be manufactured by this embodiment uses two kinds ofinternal power sources in order to restrict the increase of a fieldintensity resulting from miniaturization of elements. In other words, arelatively higher voltage is applied to the gate electrode of each MOStransistor constituting the peripheral circuit section while arelatively lower voltage is applied to the gate electrode of each MOStransistor constituting the memory cell array section. Therefore, thegate oxide film of each MOS transistor must have a film thicknesssuitable for each impression voltage. For instance, the film thicknessis preferably about 30 nm for the impressed voltage of 20 V and about 11nm for the impressed voltage of 3.3 V.

106. Therefore, the manufacturing method of this embodiment isolates theperipheral circuit section and the memory cell array section from eachother by the LOCOS method and the field-shield method in the same way asin the first to fifth embodiments, and manufactures the DRAM, whichforms the gate oxide films of both sections to the most suitable filmthickness for the respective active elements, by a minimum necessarynumber of process steps while preventing defects such as short-circuit.

107. The DRAM according to this embodiment is manufactured in thefollowing way. First, as shown in FIG. 7a, an N type impurity such asphosphorus (P) is implanted into the peripheral circuit formationsection 751 of the P type silicon substrate 701 so as to form the N well731, and a P type impurity such as boron (B) is implanted into thememory array formation section 752 so as to form the P well 732. The PNjunction between these wells 731 and 732 terminates at the main surfaceof the substrate 701.

108. Next, a silicon nitride film (not shown) is patterned and formed inthe isolation region of the peripheral circuit formation section 751 andthe portion inclusive of the boundary between the N well 731 and the Pwell 732 and then selective thermal oxidation is carried out by usingthis silicon nitride film as the oxidation-resistant mask so as to formfield oxide films 702 b and 702 a having a film thickness of about 500to about 800 nm in the isolation region of the peripheral circuitformation section 751 and in the portion of the substrate 701 inclusiveof the boundary between the wells 731 and 732, respectively. The siliconnitride film is thereafter removed by wet etching by using phosphoricacid. The field oxide film 702 a covers the PN junction between thewells 731 and 732 at the main surface of the substrate 701. In otherwords, the PN junction terminates at the inner surface of the fieldoxide film 702 a.

109. Next, a gate oxide film 703 having a film thickness of about 20 toabout 30 nm is formed on the surface of each of the N well 731 and the Pwell 732, on which the field oxide film 702 a and 702 b is not formed,by thermal oxidation as shown in FIG. 7b.

110. An N type poly-silicon film (704, 705) having a film thickness ofabout 200 to about 400 nm and a silicon dioxide film 707 having a filmthickness of about 100 to about 150 nm are deposited to the entiresurface by the CVD method as shown in FIG. 7c. These silicon dioxidefilm 707 and poly-silicon film are then processed in the peripheralcircuit formation section 751 into the pattern of the gate electrode 704of the MOS transistors and into the pattern of the shield gate electrode705, in the memory cell array formation section 752. Next, a P typeimpurity ion is implanted into the N well 731 by using, as the mask, thephoto-resist (not shown) formed into a pattern covering the memory cellarray section 752, the field oxide films 702 a and 702 b and the gateelectrode 704. In consequence, a P type impurity diffusion layer havinga low concentration (LDD layer) 706 is formed in the surface of the Nwells 731 on both sides of the gate electrode 704.

111. Next, as shown in FIG. 7d, a silicon dioxide film 708 having a filmthickness of about 100 to about 200 nm is deposited to the entiresurface by the CVD method, and the silicon dioxide film 708 and gateoxide film 703 are etched back until the surface of the siliconsubstrate 701 is exposed in the N well 731 and the P well 732. In thisway, a sidewall oxide film comprising the silicon dioxide film 708 isformed on the side surface of the gate electrode 704 and the silicondioxide film 707, and on the side surface of the shield gate electrode705 and the silicon dioxide film 707.

112. A gate oxide film 710 having a film thickness of about 11 nm isthen formed by thermal oxidation on the surfaces of the N and P wells731 and 732 in the regions where the silicon substrate 701 is exposed,as shown in FIG. 7e.

113. Next, as shown in FIG. 7f, a poly-silicon film having a filmthickness of about 200 to about 400 nm is deposited to the entiresurface by the CVD process and is then patterned into the pattern of thegate electrode 712 of the MOS transistor in the memory cell arrayformation section 752. Next, N type impurity ions are implanted into theP well 732 by using a photoresist (not shown) shaped into such a patternas to cover the peripheral circuit formation section 751, the shieldgate electrode 705 and the gate electrode 712 as the mask, and in thisway, the N type low concentration impurity diffusion layers (LDD layers)716 are formed in the surface portion of the P wells 732 on both sidesthe gate electrode 712.

114. Further, the silicon dioxide film formed on the entire surface isetched back, and N type impurity ions are then implanted into the P well732 by using the resulting sidewall oxide film 713 on the side surfaceof the gate electrode 712 as a new mask. In this way, a pair of N typehigh concentration impurity diffusion layers 718 which are to serve asthe source and the drain of the MOS transistor are formed on the surfaceportion of the P wells 732 on both sides of the gate electrode 712.

115. Next, P type impurity ions are implanted into the N well 731 byusing a photoresist (not shown) formed in such a manner as to cover thememory cell array formation section 752, the field oxide films 702 a and702 b, the gate electrode 704 and the silicon dioxide film 708 as themask. In this way, a pair of P type high concentration impuritydiffusion layers 714 which are to serve as the source and the drain ofthe MOS transistor are formed on the surface portion of the N wells 731on both sides of the gate electrode 704.

116. Next, a capacitor comprising a lower electrode 721 connected to oneof the source and the drain of the MOS transistor, a capacitordielectric film 723 such as an ONO film and an upper electrode opposingthe lower electrode 721 through the capacitor dielectric film 723 isformed as shown in FIG. 7g. After the entire surface is covered with aninsulating film 724, a leading-out electrode 722 is formed at thesource/drain of the MOS transistor. Thereafter, known process steps suchas the formation of a protective film are carried out, and the DRAMaccording to this embodiment is manufactured.

117. In the DRAM manufactured by the method according to thisembodiment, a low voltage of about 3.3 V obtained by lowering a 5 Vvoltage supplied from outside is applied to the gate electrode 712 ofthe MOS transistor in order to insure the reliable operation of theminiaturized MOS transistors constituting the memory cell array section(752). Therefore, the gate oxide film 710 is formed to a small thicknessof about 11 nm. On the other hand, because the 5 V voltage supplied fromoutside is as such applied to the gate electrode 704 of the MOStransistors constituting the peripheral circuit section (751), the gateoxide film 703 is formed to a relatively large thickness of about 20 toabout 30 nm in such a manner that the MOS transistors are not brokeneven when the 5 V voltage is applied. In this way, reliability of theMOS transistors can be improved.

118. In the peripheral circuit section, the MOS transistors areelectrically isolated from one another by the field oxide film 702having a relatively large film thickness and in the memory cell arraysection, on the other hand, the MOS transistors are electricallyisolated from one another by the shield gate electrode 705 kept at thesame potential as that of the P well 732, for example. Therefore,isolation can be attained by a small isolation width in the peripheralcircuit section (751) where a large number of CMOS circuits are formed,without the necessity of disposing a guard ring, etc, whereas in thememory cell array section (752) where a large number of N channel MOStransistors are formed, enlargement of the isolation width due to thebird's beaks and the narrow channel effect due to ion implantation forthe channel stop do not occur, and the leakage current of the diffusionlayers can be checked.

119. In the method of this embodiment, the gate electrode 704 and theshield gate electrode 705 are formed by patterning the same poly-siliconfilm, and the gate electrode 704 and the insulating film formed belowthe shield gate electrode 705 are the gate oxide film 703. Therefore,the DRAM of the type wherein the gate oxide films in the peripheralcircuit section (751) and the memory cell array section (752) havemutually different film thickness can be manufactured by a smallernumber of process steps.

120. Since the gate oxide film 703 is removed simultaneously withetch-back for forming the sidewall oxide film comprising the silicondioxide film 708, the shield gate electrode 705 is not exposed as thesilicon dioxide films 707 and 708 on the shield gate electrode 705 areremoved. In other words, short-circuit between the shield gate electrode705 and other conductor films can be prevented.

121. Though this embodiment relates to the manufacture of the DRAM, thepresent invention can be applied to the manufacture of non-volatilesemiconductor memory devices having floating gate type memory celltransistors, logical integrated circuit devices, and other semiconductordevices, by conducting isolation by both of the LOCOS method andfield-shield method so that the film thickness of the gate insulatingfilm is different in the respective regions.

What is claimed is:
 1. A semiconductor device comprising: a semiconductor substrate having a main surface; a field oxide film formed in said main surface of said semiconductor substrate, said field oxide film having an inner surface located within said semiconductor substrate; a first semiconductor region of a first conductivity type defined in said semiconductor substrate; a second semiconductor region of a second conductivity type defined in said semiconductor substrate, said first and second semiconductor regions forming a junction therebetween, said junction terminating at said inner surface of said field oxide film, whereby said first and second semiconductor regions are isolated from each other.
 2. A semiconductor device according to claim 1 , further comprising a connection conductor formed over said main surface of said semiconductor substrate for electrically connecting a first circuit element in said first semiconductor region and a second circuit element in said second semiconductor region, said connection conductor extending on said field oxide film to cross over said junction between said first and second semiconductor regions.
 3. A semiconductor device according to claim 2 , wherein said field oxide film has a thickness of about 150 nm to about 500 nm.
 4. A semiconductor device according to claim 1 , wherein one of said first and second semiconductor regions is a part of said semiconductor substrate and the other of said first and second semiconductor regions is a well formed in said semiconductor substrate.
 5. A semiconductor device according to claim 1 , wherein said first and second semiconductor regions are wells formed in different parts of said semiconductor substrate.
 6. A semiconductor device according to claim 1 , wherein said first semiconductor region is a relatively large well formed in said semiconductor substrate and said second semiconductor region is a relatively small well formed in said relatively large well.
 7. A semiconductor device according to claim 1 , further comprising a plurality of first circuit elements formed in said first semiconductor region, first field-shield isolation structures formed on said main surface of said semiconductor in said first semiconductor region to isolate said first circuit elements from one another, a plurality of second circuit elements formed in said second semiconductor region, and second field-shield isolation structures formed on said main surface of said semiconductor in said second semiconductor region to isolate said second circuit elements from one another.
 8. A semiconductor device according to claim 7 , wherein said first and second semiconductor regions are P-conductivity type and N-conductivity type wells formed in different portions of said semiconductor substrate, respectively, said first circuit elements includes an NMOS transistor and said second circuit elements includes a PMOS transistor, gates of said NMOS and PMOS transistors being electrically connected to each other by a connection conductor extending on said field oxide film to cross over said junction between said P-conductivity type well and said N-conductivity type well.
 9. A semiconductor device according to claim 7 , wherein said first and second semiconductor regions are P-conductivity type and N-conductivity type wells formed in different portions of said semiconductor substrate, respectively, said first circuit elements includes an array of memory cells and an NMOS transistor, and said second circuit elements includes a PMOS transistor, gates of said NMOS and PMOS transistors being connected to each other by a connection conductor extending on said field oxide film to cross over said junction between said P-conductivity type well and said N-conductivity type well to constitute a peripheral circuit for said memory cell array.
 10. A semiconductor device comprising: a semiconductor substrate having a main surface; first, second and third field oxide films formed in said main surface of said semiconductor substrate, each of said field oxide films having an inner surface located within said semiconductor substrate; first and second semiconductor regions defined in said semiconductor substrate, said first and second semiconductor regions having first and second conductivity types, respectively, and being arranged to form a first junction therebetween, said first junction terminating at said inner surface of said first field oxide film, whereby said first and second semiconductor regions are isolated from each other; a third semiconductor region having the second conductivity type and being defined in said semiconductor substrate so as to be spaced from said second semiconductor region, said second and third semiconductor regions forming second and third junctions with said semiconductor substrate, respectively, said second and third junctions terminating at said inner surface of said second field oxide film, whereby said second and third semiconductor regions are isolated from each other; and a fourth semiconductor region having the first conductivity type and being defined in said third semiconductor region to form a fourth junction therewith, said fourth junction terminating at said inner surface of said third field oxide film, whereby said fourth semiconductor region is isolated from said third semiconductor region.
 11. A semiconductor device according to claim 10 , further comprising a first connection conductor formed over said main surface of said semiconductor substrate for electrically connecting a first circuit element in said first semiconductor region and a second circuit element in said second semiconductor region, said first connection conductor extending on said first field oxide film to cross over said first junction between said first and second semiconductor regions, and a second connection conductor formed over said main surface of said semiconductor substrate for electrically connecting a third circuit element in said third semiconductor region and a fourth circuit element in said fourth semiconductor region, said second connection conductor extending on said third field oxide film to cross over said fourth junction between said third and fourth semiconductor regions.
 12. A semiconductor device according to claim 10 , wherein an array of non-volatile memory cells and a first NMOS transistor are formed in said first semiconductor region, a first PMOS transistor is formed in said second semiconductor region, a second PMOS transistor is formed in said third semiconductor region, and a second NMOS transistor is formed in said fourth semiconductor region, gates of said first NMOS and second PMOS transistors being connected to each other by a first connection conductor extending on said first field oxide film to cross over said first junction between said first and second semiconductor regions, gates of said second PMOS and second NMOS transistors being connected to each other by a second connection conductor extending on said third field oxide film to cross over said fourth junction between said third and fourth semiconductor regions.
 13. A semiconductor device comprising: a semiconductor substrate having a main surface; a first field oxide film and a plurality of second field oxide films formed in said main surface of said semiconductor substrate, said field oxide films having an inner surface located within said semiconductor substrate; a first semiconductor region of a first conductivity type defined in said semiconductor substrate and constituting a memory cell array section in which memory cells are formed and isolated from one another by field-shield isolation structures provided therebetween on said first semiconductor region; a plurality of second semiconductor regions defined in said semiconductor substrate and constituting a peripheral circuit section, one of said second semiconductor regions having a second conductivity type and being arranged to form a first junction with said first semiconductor region, said first junction terminating at said inner surface of said first field oxide film, whereby said first semiconductor region and said one second semiconductor region are isolated from each other, said second semiconductor regions having one of said first and second conductivity types and forming second junctions with adjacent ones of the second semiconductor regions, said second junctions terminating at said inner surfaces of said second field oxide films, whereby said second semiconductor regions are isolated from each other.
 14. A semiconductor device according to claim 13 , wherein said memory cell array section in said first semiconductor region includes memory cells of a dynamic random access memory.
 15. A semiconductor device according to claim 13 , wherein said memory cell array section in said first semiconductor region includes memory cells of a non-volatile memory.
 16. A semiconductor device comprising: a semiconductor substrate having a main surface; a first field oxide film having an inner surface located within said semiconductor substrate; a first semiconductor region of a first conductivity type defined in said semiconductor substrate and constituting a memory cell array section in which memory cells are formed and isolated with field-shield isolation structures provided therebetween on said first semiconductor region; a second semiconductor region of a second conductivity type defined in said semiconductor substrate and constituting a peripheral circuit section, said second semiconductor region being arranged to form a junction with said first semiconductor region, said junction terminating at said inner surface of said first field oxide film, whereby said first semiconductor region and said second semiconductor region are isolated from each other; and a plurality of second field oxide films formed in said second semiconductor region of said semiconductor substrate.
 17. A semiconductor device according to claim 16 , wherein said memory cell array section in said first semiconductor region includes memory cells of a dynamic random access memory.
 18. A method of manufacturing a semiconductor device comprising the steps of: preparing a semiconductor substrate having a main surface; defining a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions in said semiconductor substrate, one of said second semiconductor regions having a second conductivity type and being arranged to form a first junction with said first semiconductor region, said first junction terminating at said main surface of said semiconductor substrate, said second semiconductor regions having one of said first and second conductivity types and forming second junctions with adjacent ones of the second semiconductor regions, said second junctions terminating at said main surface of said semiconductor substrate; forming a first field oxide film to cover said first junction at said main surface of said semiconductor substrate and a plurality of second field oxide films to cover said second junctions at said main surface of said semiconductor substrate; forming at least one field-shield isolation structure on said first semiconductor region of said semiconductor substrate; and forming first circuit elements at said first semiconductor region and second circuit elements at said second semiconductor regions.
 19. A method of manufacturing a semiconductor device comprising the steps of: preparing a semiconductor substrate having a main surface; defining a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type in said semiconductor substrate, said first and second semiconductor regions forming a junction therebetween, said junction terminating at said main surface of said semiconductor substrate; forming a first field oxide film to cover said junction at said main surface of said semiconductor substrate and a plurality of second field oxide films in said second semiconductor region of said semiconductor substrate; forming at least one field-shield isolation structure on said first semiconductor region of said semiconductor substrate; and forming first circuit elements at said first semiconductor region and second circuit elements at said second semiconductor region.
 20. A method of manufacturing a semiconductor device having an isolation structure using a field oxide film and an isolation structure using a shield gate electrode, comprising the steps of: forming in serial order a first insulating film, a poly-silicon film and an oxidation prevention film on a main surface of a semiconductor substrate; removing said oxidation prevention film over the portion of said substrate at which a field oxide film is to be formed; selectively oxidizing said substrate by using said remaining oxidation prevention film as a mask and forming said field oxide film; processing said poly-silicon film into the pattern of a shield gate electrode; and forming a second insulating film on the side surface of said poly-silicon film having the pattern of said shield gate electrode.
 21. A method of manufacturing a semiconductor device according to claim 20 , further comprising the steps of: removing, after said field oxide film has been formed, said oxidation prevention film; and forming further a third insulating film on said poly-silicon film; and wherein said second insulating film is formed also on the side surface of said third insulating film.
 22. A method of manufacturing a semiconductor device according to claim 20 , wherein said oxidation prevention film is used as said second insulating film.
 23. A method of manufacturing a semiconductor device having an isolation structure using a field oxide film and an isolation structure using a shield gate electrode, comprising the steps of: forming field oxide films at a main surface of a semiconductor substrate by selective thermal oxidation; forming a first gate insulating film at the main surface of said substrate at portion where said field oxide films are not formed; patterning and forming a first conductor film to serve as a first gate electrode and a shield gate electrode on said first gate insulating film; removing said first gate insulating film in a region where said first conductor film is not formed to expose said substrate; forming a second gate insulating film on said substrate so exposed; and patterning and forming a second conductor film to serve as a second gate electrode on said second gate insulating film.
 24. A method of manufacturing a semiconductor device according to claim 23 , wherein said second gate insulating film is thinner than said first gate insulating film.
 25. A semiconductor device comprising a semiconductor substrate, first and second wells of first and second conductivity types formed so as to be adjacent to each other in a surface portion of said substrate, and a plurality of MOS transistors formed in at least one of said wells, each of said transistors having source/drain regions of a conductivity type opposite to that of said one well, wherein: said MOS transistors are electrically isolated from one another by field-shield isolation structures; and said first and second wells are electrically isolated from each other by a first field oxide film.
 26. A semiconductor device according to claim 25 , wherein at least one MOS transistor is formed in the other of said first and second wells, and one of the transistors in the first well and one of the transistors in the second well have their gates electrically connected to each other by a connection conductor extending on said first field oxide film.
 27. A semiconductor device according to claim 25 , further comprising a third well of the first conductivity type formed in the surface portion of the substrate and a fourth well of the second conductivity type formed in the surface portion of the substrate in said third well, said fourth well being to be kept at a potential of a polarity opposite to that of a power supply potential to the semiconductor device, wherein said third and fourth wells are electrically isolated from each other by a second field oxide film.
 28. A semiconductor device according to claim 27 , wherein a MOS transistor is formed in each of said third and fourth wells, and the transistors in the third and fourth wells have their gates electrically connected to each other by a connection conductor extending on said second field oxide film.
 29. A semiconductor device comprising a semiconductor substrate and a plurality of wells formed in a surface portion of said substrate, wherein: each of said wells is electrically isolated from a different one of the wells and from said semiconductor substrate by a field oxide film, and elements formed in said wells are electrically isolated from one another by field-shield isolation structures.
 30. A semiconductor device comprising a first section including first conduction type MOS transistors and a second section including a first conduction type MOS transistor and a second conduction type MOS transistor, wherein the transistors in said first section are electrically isolated from one another by field-shield isolation structures, and the transistors in said second section are electrically isolated from one another by a field oxide film.
 31. A semiconductor device according to claim 30 , wherein said first section is a DRAM cell section and said second section is a peripheral circuit section for said DRAM cell section.
 32. A semiconductor device according to claim 30 , wherein said peripheral circuit section in said second section includes CMOS circuits. 